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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Features
e·MMC™ Memory
MTFC2GMDEA-0M WT, MTFC4GLDEA-0M WT, MTFC4GMDEA-1M WT,
MTFC8GLDEA-1M WT, MTFC16GJDEC-2M WT, MTFC32GJDED-3M WT,
MTFC64GJDDN-3M WT
Features
Figure 1: Micron e·MMC Device
• MultiMediaCard (MMC) controller and NAND Flash
• 153- or 169-ball WFBGA/VFBGA/LFBGA (RoHS 6/6compliant)
• VCC: 2.7–3.6V
• VCCQ (dual voltage): 1.65–1.95V; 2.7–3.6V
• Temperature ranges
– Operating temperature: –25˚C to +85˚C
– Storage temperature: –40˚C to +85˚C
• Typical current consumption
– Standby current: 110µA for 2GB, 120µA for 4GB,
8GB, 16GB; 140µA for 32G; 160µA for 64GB
– Active current (RMS): 70mA (2GB); 80mA (4GB,
8GB, 16GB, 32GB, 64GB)
MMC
power
NAND Flash
power
MMC controller
MMC
interface
NAND Flash
MMC-Specific Features
• JEDEC/MMC standard version 4.41-compliant
(JEDEC Standard No. 84-A441) – SPI mode not
supported (see www.jedec.org/sites/default/files/
docs/JESD84-A441.pdf)
– Advanced 11-signal interface
– x1, x4, and x8 I/Os, selectable by host
– MMC mode operation
– Command classes: class 0 (basic); class 2 (block
read); class 4 (block write); class 5 (erase);
class 6 (write protection); class 7 (lock card)
– MMCplus™ and MMCmobile™ protocols
– Temporary write protection
– 52 MHz clock speed (MAX)
– Boot operation (high-speed boot)
– Sleep mode
– Replay-protected memory block (RPMB)
– Secure erase and trim
– Hardware reset signal
– Multiple partitions with enhanced attribute
– Permanent and power-on write protection
– Double data rate (DDR) function
– High-priority interrupt (HPI)
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
MMC-Specific Features (Continued)
– Enhanced reliable write
– Configurable reliability settings
– Background operation
– Fully enhanced configurable
– Backward-compatible with previous MMC
modes
• ECC and block management implemented
1
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Products and specifications discussed herein are subject to change by Micron without notice.
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Features
e·MMC Performance
Table 1: MLC Partition Performance
Part Number
MTFC2GMDEA-0M WT
MTFC4GLDEA-0M WT
MTFC4GMDEA-1M WT
MTFC8GLDEA-1M WT
MTFC16GJDEC-2M WT
MTFC32GJDED-3M WT
MTFC64GJDDN-3M WT
Units
Sequential write
6.6
13.5
20
MB/s
Sequential read
30
44
44
MB/s
Condition
Random write
90
90
90
IOPs
Random read
1080
1080
1100
IOPs
Note:
1. Bus in x8 I/O mode. Sequential access of 1MB chunk; random access of 4KB chunk. Additional performance
data, such as power consumption or timing for different device modes, will be provided in a separate document upon customer request.
Ordering Information
Table 2: Ordering Information
NAND Flash
Type
Base Part Number
Density
Package
MTFC2GMDEA-0M WT
2GB
153-ball WFBGA
11.5mm x 13.0mm x 0.8mm
1 x 16Gb, MLC, 25nm
153-ball WFBGA
11.5mm x 13.0mm x 0.8mm
1 x 32Gb, MLC, 25nm
153-ball WFBGA
11.5mm x 13.0mm x 0.8mm
2 x 16Gb, MLC, 25nm
153-ball WFBGA
11.5mm x 13.0mm x 0.8mm
2 x 32Gb, MLC, 25nm
169-ball WFBGA
14.0mm x 18.0mm x 0.8mm
2 x 64Gb, MLC, 25nm
169-ball VFBGA
14.0mm x 18.0mm x 1.0mm
4 x 64Gb, MLC, 25nm
169-ball LFBGA
14.0mm x 18.0mm x 1.4mm
8 x 64Gb, MLC, 25nm
MTFC4GLDEA-0M WT
MTFC4GMDEA-1M WT
MTFC8GLDEA-1M WT
MTFC16GJDEC-2M WT
MTFC32GJDED-3M WT
MTFC64GJDDN-3M WT
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
4GB
4GB
8GB
16GB
32GB
64GB
2
Shipping Media
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
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Features
Part Numbering Information
Micron®e·MMC memory devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 2: Marketing Part Number Chart
MT FC xx
x
x
xx - xx xx
Micron Technology
FC = NAND Flash + Controller
NAND Flash Density
NAND Flash Component
Controller ID
Package Codes
Note:
x
ES
Design Revision
Production Status
Wafer Process Applied
Operating Temperature Range
Special Options
1. Not all combinations are necessarily available. For a list of available devices or for further information on
any aspect of these products, please contact your nearest Micron sales office.
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
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General Description
General Description
Micron e·MMC is a communication and mass data storage device that includes a MultiMediaCard (MMC) interface, a NAND Flash component, and a controller on an advanced 11-signal bus, which is compliant with the MMC system specification. Its low
cost, small size, Flash technology independence, and high data throughput make
e·MMC ideal for embedded applications like set-top boxes, digital cameras/camcorders, digital TVs, and a variety other consumer products.
The nonvolatile e·MMC draws no power to maintain stored data, delivers high performance across a wide range of operating temperatures, and resists shock and vibration disruption.
PDF: 09005aef8523cb32
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Signal Descriptions
Signal Descriptions
Table 3: Signal Descriptions
Symbol
Type
Description
CLK
Input
Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The
frequency can vary between the minimum and the maximum clock frequency.
RST_n
Input
Reset: The RST_n signal is used by the host for resetting the device, moving the device to the preidle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD
register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.
CMD
I/O
Command: This signal is a bidirectional command channel used for command and response transfers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating
Modes). Commands are sent from the MMC host to the device, and responses are sent from the
device to the host.
DAT[7:0]
I/O
Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By default, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The
MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode)
or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immediately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the
DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the
DAT[7:1] lines.
VCC
Supply
VCC: NAND interface (I/F) I/O and NAND Flash power supply.
VCCQ
Supply
VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.
VSS1
Supply
VSS: NAND I/F I/O and NAND Flash ground connection.
VSSQ1
Supply
VSSQ: e·MMC controller core and e·MMC I/F ground connection.
VDDIM
Internal voltage node: At least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF capacitor is recommended. Do not tie to supply voltage or ground.
NC
–
No connect: No internal connection is present.
RFU
–
Reserved for future use: No internal connection is present. Leave it floating externally.
Note:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. VSS and VSSQ are connected internally.
5
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
153-Ball Signal Assignments
153-Ball Signal Assignments
Figure 3: 153-Ball FBGA (Top View, Ball Down)
1
2
3
A
NC
NC
DAT0
B
NC
C
6
7
8
9
10
11
12
13
14
RFU
RFU
NC
NC
NC
NC
NC
NC
NC
DAT3 DAT4
DAT5 DAT6 DAT7
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDIM
NC
VSSQ
VCCQ
NC
NC
NC
NC
NC
NC
NC
NC
D
NC
NC
NC
NC
NC
NC
NC
E
NC
NC
NC
RFU
RFU
NC
NC
NC
F
NC
NC
NC
VCC
RFU
NC
NC
NC
G
NC
NC
RFU
VSS
RFU
NC
NC
NC
H
NC
NC
NC
RFU
VSS
NC
NC
NC
J
NC
NC
NC
RFU
VCC
NC
NC
NC
K
NC
NC
NC
RST_n
RFU
NC
NC
NC
L
NC
NC
NC
NC
NC
NC
M
NC
NC
NC
VCCQ
CMD
CLK
NC
NC
NC
NC
NC
NC
NC
NC
N
NC
VSSQ
NC
VCCQ
VSSQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
P
NC
NC
VCCQ
VSSQ
VCCQ
VSSQ
RFU
NC
NC
RFU
NC
NC
NC
NC
Notes:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
4
5
DAT1 DAT2
RFU
VCC
RFU
VSS
RFU
RFU
VSS
RFU
VCC
1. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the previous specifications could have been connected to ground on the system board. To enable new feature introduction, some of these balls are assigned as RFU in the v4.4 mechanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
2. VCC, VCCQ, VSS, and VSSQ balls must all be connected.
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
169-Ball Signal Assignments
169-Ball Signal Assignments
Figure 4: 169-Ball FBGA (Top View, Ball Down)
1
2
3
A
4
5
7
8
9
10
11
12
13
14
NC
NC
NC
NC
B
6
NC
NC
C
D
NC
NC
E
F
G
H
NC
J
NC
K
RFU
RFU
NC
NC
NC
NC
NC
NC
NC
DAT3 DAT4
DAT5 DAT6 DAT7
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDIM
NC
VSSQ
VCCQ
NC
NC
NC
NC
NC
NC
NC
NC
L
NC
NC
NC
NC
NC
NC
NC
M
NC
NC
NC
RFU
RFU
NC
NC
NC
N
NC
NC
NC
VCC
RFU
NC
NC
NC
P
NC
NC
RFU
VSS
RFU
NC
NC
NC
R
NC
NC
NC
RFU
VSS
NC
NC
NC
T
NC
NC
NC
RFU
VCC
NC
NC
NC
U
NC
NC
NC
RST_n
RFU
NC
NC
NC
V
NC
NC
NC
NC
NC
NC
W
NC
NC
NC
VCCQ
CMD
CLK
NC
NC
NC
NC
NC
NC
NC
NC
Y
NC
VSSQ
NC
VCCQ
VSSQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
AA
NC
NC
VCCQ
VSSQ
VCCQ
VSSQ
RFU
NC
NC
RFU
NC
NC
NC
NC
NC
DAT0
DAT1 DAT2
RFU
VCC
RFU
VSS
RFU
RFU
VSS
RFU
VCC
AB
AC
AD
AE
NC
NC
AF
AG
AH
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
NC
NC
NC
NC
NC
7
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169-Ball Signal Assignments
Notes:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. Empty balls do not denote actual solder balls; they are position indicators only.
2. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the previous specifications could have been connected to ground on the system board. To enable new feature introduction, some of these balls are assigned as RFU in the v4.4 mechanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
3. VCC, VCCQ, VSS, and VSSQ balls must all be connected.
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Package Dimensions
Package Dimensions
Figure 5: 153-Ball WFBGA – 11.5mm x 13.0mm x 0.8mm (Package Code: EA)
Seating plane
A
153X Ø0.30
Dimensions apply
to solder balls postreflow on Ø0.30
SMD ball pads.
0.08 A
Ball A1 ID
(covered by SR)
Ball A1 ID
14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
6.5 CTR
13 ±0.1
0.5 TYP
0.5 TYP
0.7 ±0.1
6.5 CTR
0.17 MIN
11.5 ±0.1
Note:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. Dimensions are in millimeters.
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Package Dimensions
Figure 6: 169-Ball WFBGA – 14.0mm x 18.00mm x 0.8mm (Package Code: EC)
Seating plane
A
169X Ø0.3
Dimensions apply to
solder balls post-reflow
on Ø0.30 SMD OSP ball
pads.
0.08 A
Ball A1 ID
Ball A1 ID
14 12 10 8 6 4 2
13 11 9 7 5 3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
13.5 CTR
6.5 CTR
18 ±0.1
0.7 ±0.1
0.5 TYP
0.5 TYP
6.5 CTR
0.17 MIN
14 ±0.1
Note:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. Dimensions are in millimeters.
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Package Dimensions
Figure 7: 169-Ball VFBGA – 14.0mm x 18.00mm x 1.0mm (Package Code: ED)
Seating plane
A
169X Ø0.3
Dimensions apply to
solder balls post-reflow
on Ø0.30 SMD ball pads.
0.08 A
Ball A1 ID
Ball A1 ID
14 12 10 8 6 4 2
13 11 9 7 5 3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
13.5 CTR
6.5 CTR
18 ±0.1
0.5 TYP
0.9 ±0.1
0.5 TYP
6.5 CTR
0.17 MIN
14 ±0.1
Note:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. Dimensions are in millimeters.
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Package Dimensions
Figure 8: 169-Ball LFBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DN)
Seating plane
A
169X Ø0.3
Dimensions apply
to solder balls postreflow on Ø0.30 SMD
ball pads.
0.08 A
Ball A1 ID
(covered by SR)
Ball A1 ID
14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
13.5 CTR
6.5 CTR
18 ±0.1
0.5 TYP
1.3 ±0.1
0.5 TYP
6.5 CTR
0.16 MIN
14 ±0.1
Note:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. Dimensions are in millimeters.
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Architecture
Architecture
Figure 9: e·MMC Functional Block Diagram
e·MMC
MMC
controller
RST_n
VDDIM
VCCQ
Registers
CMD
CLK
VCC
DAT[7:0]
OCR
CSD
RCA
CID
ECSD
DSR
VSS1
VSSQ1
NAND Flash
Note:
1. VSS and VSSQ are internally connected.
MMC Protocol Independent of NAND Flash Technology
The MMC specification defines the communication protocol between a host and a device. The protocol is independent of the NAND Flash features included in the device.
The device has an intelligent on-board controller that manages the MMC communication protocol.
The controller also handles block management functions such as logical block allocation and wear leveling. These management functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
The device handles these management functions internally, making them invisible to
the host processor.
Defect and Error Management
Micron e·MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
space allocated for the user.
The device also includes a built-in error correction code (ECC) algorithm to ensure that
data integrity is maintained.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.
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CID Register
CID Register
The card identification (CID) register is 128 bits wide. It contains the device identification information used during the card identification phase as required by e·MMC protocol. Each device is created with a unique identification number.
Table 4: CID Register Field Parameters
Name
Field
Width
CID Bits
CID Value
Manufacturer ID
MID
8
[127:120]
FEh
Reserved
–
6
[119:114]
–
Card/BGA
CBX
2
[113:112]
01h
OEM/application ID
OID
8
[111:104]
–
Product name
PNM
48
[103:56]
MMC02G
MMC04G
MMC08G
MMC16G
MMC32G
MMC64G
Product revision
PRV
8
[55:48]
–
Product serial number
PSN
32
[47:16]
–
Manufacturing date
MDT
8
[15:8]
–
CRC7 checksum
CRC
7
[7:1]
–
–
1
0
–
Not used; always 1
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CSD Register
CSD Register
The card-specific data (CSD) register provides information about accessing the device
contents. The CSD register defines the data format, error correction type, maximum data access time, and data transfer speed, as well as whether the DS register can be used.
The programmable part of the register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD (CMD27) command.
Table 5: CSD Register Field Parameters
Name
Field
Width
Cell
Type1
CSD
Bits
CSD
Value
CSD structure
CSD_STRUCTURE
2
R
[127:126]
03h
System specification version
SPEC_VERS
4
R
[125:122]
4h
2
TBD
[121:120]
–
Reserved2
–
Data read access time 1
TAAC
8
R
[119:112]
4Fh
Data read access time 2 in CLK
cycles (NSAC × 100)
NSAC
8
R
[111:104]
01h
Maximum bus clock frequency
TRAN_SPEED
8
R
[103:96]
32h
Card command classes
CCC
12
R
[95:84]
0F5h
Maximum read data block
length
READ_BL_LEN
4
R
[83:80]
0Ah
Partial blocks for reads supported
READ_BL_PARTIAL
1
R
79
0h
Write block misalignment
WRITE_BLK_MISALIGN
1
R
78
0h
Read block misalignment
READ_BLK_MISALIGN
77
R
77
0h
DS register implemented
DSR_IMP
1
R
76
1h
–
2
R
[75:74]
–
2GB
12
R
[73:62]
E4Fh
4GB,
4GB,
8GB,
16GB,
32GB,
64GB
Reserved
Device size
2GB
C_SIZE
09h
4GB,
4GB,
8GB,
16GB,
32GB,
64GB
FFFh
Maximum read current at
VDD,min
VDD_R_CURR_MIN
3
R
[61:59]
7h
Maximum read current at
VDD,max
VDD_R_CURR_MAX
3
R
[58:56]
7h
Maximum write current at
VDD,min
VDD_W_CURR_MIN
3
R
[55:53]
7h
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
CSD Register
Table 5: CSD Register Field Parameters (Continued)
Name
Field
Width
Cell
Type1
CSD
Bits
CSD
Value
Maximum write current at
VDD,max
VDD_W_CURR_MAX
3
R
[52:50]
7h
Device size multiplier
C_SIZE_MULT
3
R
[49:47]
7h
Erase group size
ERASE_GRP_SIZE
5
R
[46:42]
1Fh
Erase group size multiplier
ERASE_GRP_MULT
Write protect group size
WP_GRP_SIZE
2GB
5
R
[41:37]
1Fh
5
R
[36:32]
03h
4GB,
4GB
07h
8GB
0Fh
16GB,
32GB,
64GB
1Fh
Write protect group enable
WP_GRP_ENABLE
1
R
31
1h
Manufacturer default ECC
DEFAULT_ECC
2
R
[30:29]
0h
Write-speed factor
R2W_FACTOR
3
R
[28:26]
2h
Maximum write data block
length
WRITE_BL_LEN
4
R
[25:22]
9h
Partial blocks for writes supported
WRITE_BL_PARTIAL
1
R
21
0h
4
R
[20:17]
–
Reserved
–
Content protection application
CONTENT_PROT_APP
1
R
16
0h
File-format group
FILE_FORMAT_GRP
1
R/W
15
0h
Copy flag (OTP)
COPY
1
R/W
14
0h
Permanent write protection
PERM_WRITE_PROTECT
1
R/W
13
0h
Temporary write protection
TMP_WRITE_PROTECT
1
R/W/E
12
0h
File format
FILE_FORMAT
2
R/W
[11:10]
0h
ECC
ECC
2
R/W/E
[9:8]
0h
CRC
CRC
7
R/W/E
[7:1]
–
1
–
0
1h
Not used; always 1
–
Notes:
1. R = Read-only
R/W = One-time programmable and readable
R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n
signal, and any CMD0 reset, and readable
TBD = To be determined
2. Reserved bits should be read as 0.
3. The IPEAK, max driving capability can be modified according to the actual capacitive load
on the e·MMC interface signals in the user application board, using CMD4.
CMD4 Argument
0x01000000
0x02000000
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
Driving Capability (mA)
4
8
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CSD Register
0x04000000
0x08000000
0x10000000
0x20000000
0x40000000
0x80000000
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
12 (default)
16
20
24
28
32
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ECSD Register
ECSD Register
The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This segment defines device capabilities and cannot be modified by the host. The lower 192
bytes are the modes segment. The modes segment defines the configuration in which
the device is working. The host can change the properties of modes segments using the
SWITCH command.
Table 6: ECSD Register Field Parameters
Name
Field
Size
(Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
–
7
–
[511:505]
–
Properties Segment
Reserved2
Supported command sets
S_CMD_SET
1
R
504
1h
HPI features
HPI_FEATURES
1
R
503
3h
1
R
502
1h
255
–
[501:247]
–
Background operations support BKOPS_SUPPORT
Reserved
–
Background operations status
BKOPS_STATUS
1
R
246
0h
Number of correctly programmed sectors
CORRECTLY_PRG_
SECTORS_NUM
4
R
[245:242]
–
First initialization time after
partitioning
(first CMD1 to device ready)
INI_TIMEOUT_PA 2GB
1
R
241
7Ah
Reserved
4GB
F6h
4GB
7Ah
8GB,
16GB
F6h
32GB,
64GB
FFh
–
1
–
240
–
Power class for 52 MHz, DDR at PWR_CL_DDR_52_360
3.6V3
1
R
239
0h
Power class for 52 MHz, DDR at PWR_CL_DDR_52_195
1.95V3
1
R
238
0h
Reserved
2
–
[237:236]
–
1
R
235
0h
Minimum read performance for MIN_PERF_DDR_R_8_52
8-bit at 52 MHz in DDR mode
1
R
234
0h
Reserved
1
–
233
–
Minimum write performance
for 8-bit at 52 MHz in DDR
mode
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
–
MIN_PERF_DDR_W_8_52
–
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Name
TRIM multiplier
Field
TRIM_MULT
2GB
4GB,
4GB,
8GB
Size
(Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
1
R
232
06h
16GB,
32GB,
64GB
0Fh
Secure feature support
SEC_FEATURE_SUPPORT
1
R
231
15h
SECURE ERASE multiplier
SEC_ERASE_MULT 2GB
4GB,
4GB,
8GB
1
R
230
02h
16GB,
32GB,
64GB
SECURE TRIM multiplier
SEC_TRIM_MULT
06h
2GB
4GB,
4GB,
8GB
1
R
229
16GB,
32GB,
64GB
Boot information
Boot partition size
Access size
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
09h
BOOT_INFO
Reserved
–
BOOT_SIZE_MULT 2GB,
4GB
ACC_SIZE
03h
1
R
228
7h
1
–
227
–
1
R
226
08h
4GB,
8GB
10h
16GB
20h
32GB,
64GB
40h
2GB,
4GB
1
R
225
05h
4GB,
8GB
06h
16GB,
32GB,
64GB
07h
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Name
High-capacity erase unit size
Field
HC_ERASE_GRP_S 2GB
IZE
4GB
Size
(Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
1
R
224
00h
04h
4GB,
8GB
08h
16GB,
32GB,
64GB
10h
High-capacity erase timeout
ERASE_TIMEOUT_MULT
1
R
223
01h
Reliable write-sector count
REL_WR_SEC_C
1
R
222
01h
High-capacity write protect
group size
HC_WP_GRP_SIZE 2GB
1
R
221
00h
4GB
02h
4GB
01h
8GB,
16GB
02h
32GB
04h
64GB
08h
Sleep current (VCC)
S_C_VCC
1
R
220
08h
Sleep current (VCCQ)
S_C_VCCQ
1
R
219
08h
1
–
218
–
Reserved
Sleep/awake timeout
–
S_A_TIMEOUT
Reserved
Sector count
SEC_COUNT
1
R
217
10h
–
1
–
216
–
2GB
4
R
[215:212]
00000000h
4GB
00750000h
4GB
00728000h
8GB
00EA0000h
16GB
01D40000h
32GB
03B20000h
64GB
Reserved
07700000h
1
–
211
–
1
R
210
08h
Minimum read performance for MIN_PERF_R_8_52
8-bit at 52 MHz
1
R
209
08h
Minimum write performance
MIN_PERF_W_8_26_4_52
for 8-bit at 26 MHz and 4-bit at
52 MHz
1
R
208
08h
Minimum read performance for MIN_PERF_R_8_26_4_52
8-bit at 26 MHz and 4-bit at 52
MHz
1
R
207
08h
Minimum write performance
for 8-bit at 52 MHz
PDF: 09005aef8523cb32
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–
MIN_PERF_W_8_52
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Name
Field
Minimum write performance
for 4-bit at 26 MHz
MIN_PERF_W_4_26
Minimum read performance for MIN_PERF_R_4_26
4-bit at 26 MHz
Reserved
Power class for 26 MHz at
–
3.6V3
Size
(Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
1
R
206
08h
1
R
205
08h
1
–
204
–
PWR_CL_26_360
1
R
203
00h
Power class for 52 MHz at 3.6V3 PWR_CL_52_360
1
R
202
00h
Power class for 26 MHz at
1.95V3
PWR_CL_26_195
1
R
201
00h
Power class for 52 MHz at
1.95V3
PWR_CL_52_195
1
R
200
00h
Partition switching timing
PARTITION_SWITCH_TIME
1
R
199
1h
Out-of-interrupt busy timing
OUT_OF_INTERRUPT_TIME
1
R
198
02h
1
–
197
–
1
R
196
07h
1
–
195
–
1
R
194
2h
1
–
193
–
EXT_CSD_REV
1
R
192
5h
CMD_SET
1
R/W/E_P
191
0h
1
–
190
–
1
R
189
0h
1
–
188
–
1
R/W/E_P
187
0h
1
–
186
–
1
R/W/E_P
185
0h
1
–
184
–
1
W/E_P
183
0h
1
–
182
–
1
R
181
0h
Reserved
Card type
–
CARD_TYPE
Reserved
CSD structure version
–
CSD_STRUCTURE
Reserved
Extended CSD revision
–
Modes Segment
Command set
Reserved
Command set revision
–
CMD_SET_REV
Reserved
Power class
–
POWER_CLASS
Reserved
High-speed interface timing
–
HS_TIMING
Reserved
Bus width mode
–
BUS_WIDTH
Reserved
Erased memory content
–
ERASED_MEM_CONT
Reserved
1
–
180
–
Partition configuration
PARTITION_CONFIG
1
R/W/E,
R/W/E_P
179
0h
Boot configuration protection
BOOT_CONFIG_PROT
1
R/W,
R/W/C_P
178
0h
Boot bus width
BOOT_BUS_WIDTH
1
R/W/E
177
0h
1
–
176
–
Reserved
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
–
–
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Name
High-density erase group definition
Field
ERASE_GROUP_DEF
Reserved
–
Boot area write protection reg- BOOT_WP
ister
Reserved
User write protection register
–
USER_WP
Reserved
–
Size
(Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
1
R/W/E_P
175
00h
1
–
174
–
1
R/W,
R/W/C_P
173
0h
1
–
172
–
1
R/W,
R/W/C_P,
R/W/E_P
171
0h
1
–
170
–
R/W
169
0h
Firmware configuration
FW_CONFIG
1
RPMB size
RPMB_SIZE_MULT
1
R
168
1h
Write reliability setting register3
WR_REL_SET
1
R/W
167
00h4
1
R
166
05h
1
–
165
–
Manually start background op- BKOPS_START
erations
1
W/E_P
164
–
Enable background operations
handshake
BKOPS_EN
1
R/W
163
0h
Hardware reset function
RST_n_FUNCTION
1
R/W
162
0h
HPI management
HPI_MGMT
1
R/W/E_P
161
0h
Write reliability parameter reg- WR_REL_PARAM
ister
Reserved
–
Partitioning support
PARTITIONING_SUPPORT
1
R
160
3h
Maximum enhanced area size
MAX_ENH_SIZE_
MULT
3
R
[159:157]
0001CAh
2GB
4GB
0001D4h
4GB
0001CAh
8GB,
16GB
0001D4h
32GB
0001D9h
64GB
0001DCh
Partitions attribute
PARTITIONS_ATTRIBUTE
1
R/W
Partitioning setting
General-purpose partition size
PARTITION_SETTING_COMPLETED
1
GP_SIZE_MULT
12
Enhanced user data area size
ENH_SIZE_MULT
Enhanced user data start address
ENH_START_ADDR
Reserved
Bad block management mode
PDF: 09005aef8523cb32
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–
SEC_BAD_BLK_MGMNT
22
156
0h
R/W
155
0h
R/W
[154:143]
0h
3
R/W
[142:140]
0h
4
R/W
[139:136]
0h
1
–
135
–
1
R/W
134
0h
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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Name
Reserved
Notes:
Field
Size
(Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
–
134
–
[133:0]
–
1. R = Read-only
R/W = One-time programmable and readable
R/W/E = Multiple writable with the value kept after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the
RST_n signal (the value not cleared by CMD0 reset) and readable
R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n
signal, and any CMD0 reset, and not readable
TBD = To be determined
2. Reserved bits should be read as 0.
3. Micron has tested power failure under best application knowledge conditions with positive results. Customers may request a dedicated test for their specific application condition.
4. Can be set to 1Fh to enable reliability settings. This byte is one-time programmable.
5. The first showing of 4GB refers to the 1-channel device, while the second showing of
4GB refers to the 2-channel device.
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
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DC Electrical Specifications – Device Power
DC Electrical Specifications – Device Power
The device current consumption for various device configurations is defined in the
power class fields of the ECSD register.
VCC is used for the NAND Flash device and its interface voltage; V CCQ is used for the
controller and the e·MMC interface voltage.
Figure 10: Device Power Diagram
VCC
VCCQ
C3
C4
C1
C2
Core regulator
NAND
control signals
C6
CLK
CMD
DAT[7:0]
NAND Flash
NAND
I/O block
C5
MMC
I/O block
VDDIM
Core
logic block
NAND
data bus
VCCQ
MMC controller
VCCQ
Table 7: Power Domains
Parameter
Symbol
Comments
Host interface
VCCQ
High voltage range = 3.3V (nominal)
Low voltage range = 1.8V (nominal)
Memory
VCC
High voltage range = 3.3V (nominal)
Internal
VDDIM
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
The internal regulator connection to an external decoupling capacitor
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DC Electrical Specifications – Device Power
Table 8: Capacitor and Resistance Specifications
Parameter
Symbol
Min
Max
Typ
Units
Notes
Pull-up resistance: CMD
R_CMD
4.7
50
10
kΩ
1
R_DAT
10
50
50
kΩ
1
R_RST_n
4.7
50
50
kΩ
2
45
55
50
Ω
3
SR_CLK
0
47
22
Ω
C1
2.2
4.7
2.2
µF
4
C2
0.1
0.22
0.1
C3
2.2
4.7
2.2
µF
5
C4
0.1
0.22
0.1
C3
2.2
4.7
4.7
µF
5
C4
0.1
0.22
0.22
C5
1
4.7
1
µF
6
C6
0.1
0.1
0.1
Pull-up resistance: DAT[7:0]
Pull-up resistance: RST_n
CLK/CMD/DAT[7:0] impedance
Serial resistance on CLK
VCCQ capacitor
VCC capacitor (≤8GB)
VCC capacitor (>8GB)
VDDIM capacitor (Creg)
Notes:
PDF: 09005aef8523cb32
emmc_2gb-64gb_ctrd_441-wt.pdf - Rev. B 9/13 EN
1. Used to prevent bus floating.
2. If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line
(Extended_CSD[162] = 00h).
3. Impedance match.
4. The coupling capacitor should be connected with VCCQ and VSSQ as closely as possible.
5. The coupling capacitor should be connected with VCC and VSS as closely as possible.
6. The coupling capacitor should be connected with VDDIM and VSS as closely as possible.
25
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Revision History
Revision History
Rev. B – 09/13
• To Production status
• Added channel note to ECSD Register
Rev. A – 03/13
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef8523cb32
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